The present invention relates to a large diameter epitaxial silicon wafer, a method for producing the same, and a substrate for an epitaxial silicon wafer.
Most of currently manufactured devices such as operational elements and memories are fabricated on a surface of a wafer, which is manufactured from a silicon single crystal that has been pulled by the Czochralski method (CZ method). In these devices, electric circuits are formed by utilizing an extremely thin surface layer of silicon wafer and operated. As means for improving quality of the surface layer and preventing latch-up, an epitaxial silicon wafer (hereafter also referred to as xe2x80x9cepi-waferxe2x80x9d) is often used.
The epi-wafer is produced by growing an epitaxial layer (hereafter also referred to as xe2x80x9cepi-layerxe2x80x9d) on a wafer sliced from a silicon single crystal grown by the CZ method or the like. So far, as concerns epi-wafer, not so much attention has been paid for the quality of mirror surface silicon wafers used as substrates, since an epi-layer is deposited thereon.
In a crystal, there are generally two kinds of point defects formed during the crystal growth, i.e., one is vacancy and the other is self interstitial atom (interstitial-Si). A region where depressions, voids and so forth generated due to missing of silicon atoms are dominantly present among the above defects is called V-region. A region where dislocations generated due to presence of excessive silicon atoms and self interstitial atoms such as aggregations of excessive silicon atoms are dominant is called as I-region. In the V-region, there are grown-in defects considered to be originated from voids, i.e., aggregations of void-type point defects, such as FPD, LSTD and COP, at a high density. In the I-region, there are present L/D (abbreviation of interstitial dislocation loop: LSEPD, LFPD and so forth) defects, which are considered to be originated from dislocation loops, at a low density.
The boundary between the V-region and the I-region in the crystal is decided by the ratio of the crystal growth rate F [mm/min] and the temperature gradient G [xc2x0 C./mm] along the crystal growth axis direction in the vicinity of the crystal growth interface, F/G (G is a value obtained by dividing the temperature difference of 12xc2x0 C. between the melting point of silicon, 1412xc2x0 C., and 1400xc2x0 C. by a distance [mm] between the points of 1412xc2x0 C. and 1400xc2x0 C. along the axial direction). If this F/G exceeds a certain value, the crystal becomes the V-region, and if F/G is lower than the certain value, the crystal becomes the I-region.
Generally, the temperature gradient G along the crystal growth axis direction shows distribution along the radial direction in the crystal growth interface, and it becomes smaller at the center and becomes larger at the periphery of the crystal (see FIG. 1). Since the crystal growth rate in a growing crystal is constant along the radial direction, distribution of F/G along the radial direction should be a reciprocal of the distribution of G along the radial direction. If F/G exceeds a certain value for the entire crystal growth interface, there is obtained a crystal that provides a wafer with no I-region for the entire plane. However, this may not usually be considered for a portion within 20 mm of the outermost periphery, since point defects can out-diffuse to the crystal surface and can be eliminated in this portion. For example, in case of a crystal having a usual resistivity (that having a resistivity of 0.03 xcexa9xc2x7cm or more in the present invention), if F/G is 0.18 mm2/xc2x0 C.xc2x7min or more for the entire inner portion except for the peripheral portion within 20 mm, there can be obtained a crystal providing the V-region for the entire plane. Conversely, if F/G is 0.18 mm2/xc2x0 C.xc2x7min or less for the entire inner portion except for the peripheral portion within 20 mm, there can be obtained a crystal providing the I-region for the entire plane.
Under such a situation as described above, in the production of large diameter crystals having a diameter of 10 inches or more, which will be a main stream in future, the difference of G between the center and periphery of a crystal becomes large, and growth rate F is decreased due to increase in solidification latent heat. Therefore, it has become difficult to attain such an F/G that the V-region should be obtained for full radius of the crystal. For this reason, the I-region and the V-region tend to coexist in a wafer plane, and most of commercially available large diameter wafers contain the I-region.
By the way, P-type low resistivity wafers having a resistivity of 0.03 xcexa9xc2x7cm or less, which are currently often used as substrates for epi-wafers, contain boron with a small covalent radius at a high concentration. Therefore, self interstitial atoms are likely to exist therein, and the value of F/G deciding the boundary of the I-region and the V-region becomes larger in connection with decrease in resistivity. Thus, most of commercially available P-type low resistivity wafers contain the I-region.
Under the recent stream of using a larger diameter of crystals and a lower temperature for the growth of epi-layers, it has become more frequent to produce epi-wafers comprising a large diameter crystal having a diameter of 10 inches or more, on which an epi-layer is grown at a lower temperature. Under such a circumstance, it has become more frequent to find, on the epi-wafers, particles that have not been observed on conventional wafers. Study of these particles has revealed that they correspond to particles that are detected on mirror wafer surfaces used as substrates by the high sensitivity particle measurement method, and they constitute projection type surface distortion observed as projections or particles when observed by AFM (atomic force microscope) or the like (they are also referred to as xe2x80x9cprojection-like particlesxe2x80x9d hereinafter).
It has been also revealed that these projections become still larger when an epitaxial layer is deposited, and they may also be detected as usual particles or the like. It has been also found that many of these projections are present in the I-region, which has conventionally been considered to have fewer defects. These projections and projection-like particles may cause breaking of wiring and so forth when an integrated circuit is formed on the wafer surface in the device production process. Therefore, they greatly affect device characteristics and reliability of devices, and thus their presence cannot be accepted in view of required quality of epi-wafers.
The present invention was accomplished in view of the problems described above, and its major object is to provide an epitaxial wafer of high quality with no projection-like particles on its epi-layer surface by forming a wafer not having the I-region for the entire surface from a single crystal of a large diameter and depositing an epitaxial layer thereon, and to produce a single crystal of a large diameter having no I-region for entire plane with good yield and high productivity, thereby improving productivity of epi-wafers and realizing cost reduction.
The present invention was accomplished in order to achieve the aforementioned object. According to the first aspect of the present invention, there is provided an epitaxial silicon wafer, which has no projections having a size of 100 nm or more and a height of 5 nm or more on an epitaxial layer. Such an epitaxial silicon wafer substantially does not have, on its epi-layer, projections or projection-like particles of the size defined above, which are harmful to quality of the wafer. Therefore, it scarcely suffer from breaking of wiring during the device production process, and thus there can be provided an epitaxial wafer of high quality, which does not adversely affect the device characteristics and the reliability of devices.
According to the second aspect of the present invention, there is provided a method for producing an epitaxial silicon wafer, wherein a silicon wafer which has no projections having a size of 100 nm or more and a height of 5 nm or more is used as a silicon wafer for an epitaxial substrate.
If a silicon wafer which has no projections having a size of 100 nm or more and a height of 5 nm or more is used for an epitaxial substrate as described above, an epitaxial silicon wafer of high quality can be produced, which does not have, on its epi-layer after epitaxial growth, projections or projection-like particles having a size of 100 nm or more and a height of 5 nm or more, which degrade device characteristics.
Further, according to the third aspect of the present invention, there is provided a method for producing an epitaxial silicon wafer, wherein a single crystal containing no I-region is used as a silicon wafer for an epitaxial substrate.
If a wafer is sliced from a single crystal containing no I-region, which is a cause of generating many projections on the epitaxial layer, and the silicon wafer having no I-region in the entire surface is used for an epitaxial substrate as described above, an epitaxial silicon wafer of high quality can be produced, which does not have, on the epitaxial layer, projections having a size of 100 nm or more and a height of 5 nm or more.
Furthermore, according to the fourth aspect of the present invention, there is provided a method for producing an epitaxial silicon wafer, wherein a silicon single crystal ingot containing no I-region is grown when a silicon single crystal is grown by the Czochralski method, and an epitaxial layer is deposited on a silicon wafer sliced from the single crystal ingot and containing no I-region for the entire plane.
If a silicon single crystal containing no I-region is grown when a silicon single crystal is grown by the CZ method, and an epitaxial layer is deposited on a silicon wafer sliced from the single crystal ingot and containing no I-region for the entire plane as described above, substantially no projections or projection-like particles are generated on the epitaxial layer, and thus an epitaxial silicon wafer of high quality can be produced.
In the above method, when the silicon single crystal is grown by the Czochralski method, a magnetic field can be applied.
By applying a magnetic field as mentioned above, convection of silicon melt along the transverse direction with respect to the magnetic line can be suppressed and hence the temperature gradient in the silicon melt can be made larger. Therefore, it becomes possible to realize a higher crystal growth rate.
In the above method, by using the growth condition of silicon single crystal F/G [mm2/xc2x0 C.xc2x7min] (F is the crystal growth rate [mm/min] and G is the temperature gradient [xc2x0 C./mm] along the crystal growth axis direction in the vicinity of the single crystal growing interface) of 0.18 mm2/xc2x0 C.xc2x7min or more, there can be grown a single crystal ingot having a resistivity of 0.03 xcexa9xc2x7cm or more and providing the V-region for an entire plane in the crystal along the radial direction.
When a single crystal to be produced has a resistivity of 0.03 xcexa9xc2x7cm or more, if a single crystal is grown with the growth condition F/G of 0.18 mm2/xc2x0 C.xc2x7min or more as described above, a single crystal ingot providing the V-region for the entire plane can be grown, and an epitaxial silicon wafer having substantially no projection-like particles can be produced by depositing an epitaxial layer on a silicon wafer sliced from the aforementioned single crystal ingot and having the V-region for the entire plane.
Furthermore, by using a growth condition F/G of silicon single crystal for satisfying the following equation, a P-type single crystal ingot having a low resistivity of 0.03 xcexa9xc2x7cm or less and having the V-region for an entire plane can be grown.
F/G greater than 720xc2x7xcfx812xe2x88x9237xc2x7xcfx81+0.65
In the equation, xcfx81 is resistivity of single crystal [xcexa9xc2x7cm], F is the single crystal growth rate [mm/min], and G is the temperature gradient [xc2x0 C./mm] along the crystal growth axis direction in the vicinity of the single crystal growing interface.
When a single crystal to be produced is a P-type crystal having a resistivity of 0.03 xcexa9xc2x7cm or less, if the single crystal is grown with the growth condition F/G satisfying the above equation in which F/G is represented as a function of the resistivity of the single crystal to be produced, a crystal ingot having the V-region for an entire plane along the radial direction of the crystal can be grown, and an epitaxial silicon wafer having substantially no projection-like particles can be produced by depositing an epitaxial layer on a silicon wafer sliced from the aforementioned single crystal ingot and having the V-region for the entire surface.
In the above method, it is desirable that the single crystal is produced by applying a horizontal magnetic field with a center magnetic field strength of 500 to 6000 Gauss.
In the MCZ method, by applying a horizontal magnetic field (henceforth also referred to as the xe2x80x9cHMCZ methodxe2x80x9d) with a center magnetic field strength of 500 to 6000 Gauss, vertical convection of the silicon melt in a crucible is efficiently suppressed and hence the amount of vaporized oxygen is suppressed in the vicinity of the crystal. Thus, the oxygen concentration distribution in a plane along the radial direction of the crystal is made more uniform, and the crystal growth at a higher growth rate can be realized without causing deformation of the crystal. Further, since the vertical convection is suppressed, the temperature gradient (dT/dZ)m of the silicon melt under the crystal can be made smaller, and thus the growth rate can be made higher.
Furthermore, it is desirable to use an internal structure of a furnace that can produce a portion having a temperature gradient G of 3.0xc2x0 C./mm or more in at least a part of distribution of the temperature gradient G along the radial direction.
It is easy to use an internal structure of a furnace providing a low G in order to obtain an F/G in the range defined above. However, it leads to reduction of productivity. In contrast, if there is used an internal structure of a furnace that can produce a portion having a temperature gradient G of 3.0xc2x0 C./mm or more in at least a part of the temperature gradient distribution along the radial direction as described above and a growth rate F that gives an F/G providing the V-region for the entire surface of a wafer, reduction of productivity can be avoided.
Further, in the above method, it is desirable to use a crystal rotation of 10 rpm or less during the growth of single crystal.
In order to obtain the V-region for the entire wafer surface, it is desirable to use a higher growth rate. However, a higher growth rate F may generate deformation of crystal. In order to suppress this deformation, it is effective to use a lower crystal rotation rate. However, a lower crystal rotation rate is generally undesirable, since it may induce unevenness of oxygen concentration within the crystal growth interface. In particular, it may cause warp of wafers in the device production process, and thus it may lead to a serious problem. However, in the present invention, since a horizontal magnetic field is applied and hence the vertical convection is suppressed, the oxygen concentration distribution in the plane is not unduly degraded even if the crystal rotation rate is lowered, and a higher growth rate may be used without generating deformation of the crystal.
Further, according to the present invention, it becomes possible to produce a large diameter single crystal ingot having a diameter of 250 mm (10 inches) or more in the production of single crystals.
If the aforementioned single crystal growth condition is satisfied according to the present invention, a single crystal having a diameter of 10 inches or more can relatively easily be grown so that it should have the V-region for an entire plane along the radial direction, and generation of projections on epi-wafers can be prevented.
Further, the epitaxial silicon wafer of the present invention is an epitaxial silicon wafer characterized by being produced by the aforementioned production method.
As described above, the epitaxial silicon wafer obtained by the method of the present invention can be an epitaxial silicon wafer of high quality that does not have projections having a size of 100 nm or more and a height of 5 nm or more on the epi-layer and does not adversely affect the characteristics and reliability of devices.
Furthermore, the substrate for an epitaxial silicon wafer of the present invention is a substrate for an epitaxial silicon wafer produced by the aforementioned production method and characterized in that it has an oxygen concentration distribution in a plane of 10% or less.
The substrate for an epitaxial silicon wafer obtained by the method of the present invention has a low oxygen concentration distribution in a plane of 10% or less as described above, and therefore it can be a substrate for an epitaxial silicon wafer of high quality that does not adversely affect the characteristics and reliability of devices.
As explained above, according to the present invention, a silicon single crystal of high quality that dose not contain the I-region for an entire plane along the radial direction of the single crystal and does not generate projections (particle-like scattering) when it is processed into an epi-wafer, which are qualitative characteristics suitable for a silicon single crystal for an epitaxial wafer substrate, can be produced with improved yield and productivity, and thus it enables marked reduction of the production cost for single crystals.
This enables providing a silicon single crystal suitable for large diameter epi-wafers, which are considered to be a mainstream in future, or suitable as a single crystal of low resistivity, which is the current mainstream. Therefore, there can be provided epitaxial silicon wafers of high quality that do not have projection or projection-like particles at low cost, and thus yield of the device production and characteristics and reliability of devices can markedly be improved.